Synchronous signals which are transferred to a semiconductor circuitry arrangement and in particular to a memory chip or the like are often subject of a storing process or latching process. Such a storing process or latching process for instance in memory chip applications is initialized and ruled by respective clock signals. After receiving e.g. multiple synchronous signals from external the respective synchronous signals to be latched and the respective latching signal or latching clock signal may suffer different delay processes when traveling along the different data line arrangements. It is therefore necessary to observe that a correct timing between the signals to be latched and the latching clock signal can be obtained or maintained. That means that a correct timing between the signals to be latched and the latching clock signal is only given if certain timing boundaries between the signals to be latched and the latching clock signal are fulfilled.
In order to adapt the delay of a latching clock signal to the delay of the signals to be latched and therefore in order to adapt respective signal phases it is known in the art to provide certain compensation strategies, for instance by applying an additional and artificial delay to the respective latching clock signal. However, in doing so the respective circuitry arrangements become comparable complex as such circuitry arrangements are built up for instance as dynamic clock alignment circuits which use delay locked loops DLL or phase locked loops PLL in each case with a dynamic feedback arrangement. In particular the involved DLL circuits and the PLL circuits and the respective dynamic feedback loops make the dynamic clock alignment circuits too complex and too area space-consuming and therefore prohibit a multiple employment or usage of such circuits within a given semiconductor circuitry.